Monolithcally integrated semiconductor component

ABSTRACT

The invention concerns a monolithically integrated semiconductor component, having a first charge carrier region ( 12 ) of a first charge carrier doping; at least two second charge carrier regions ( 14 ) with opposite charge carrier doping, patterned within the first charge carrier region ( 12 ) at a spacing from one another; and third charge carrier regions ( 16 ), with the first charge carrier doping, patterned within the second charge carrier regions ( 14 ), a PN transition ( 22 ) being short-circuited between the second charge carrier regions ( 14 ) and the third charge carrier regions ( 16 ) via a contacting area ( 20 ) (source connection), the first charge carrier region ( 12 ) being equipped with a contact ( 18 ) (drain connection), and the second charge carrier regions ( 14 ) being invertable by means of a contacting area ( 26 ) in the region between the first charge carrier region ( 12 ) and the third charge carrier region ( 16 ); and having at least one Schottky diode ( 30 ) connected in parallel with the charge carrier region ( 12 ) and the charge carrier region ( 16 ),  
     Provision is made for the first charge carrier region ( 12 ) to have a further contacting area ( 28 ), this contacting area being additionally doped near the surface, depending on the doping concentration of the first region ( 12 ), with a further near-surface charge carrier region ( 32 ) of higher concentration, so that an ohmic contact is created and is connected to the anode connection of the at least one Schottky diode ( 30 ).

FIELD OF THE INVENTION

[0001] The invention concerns a monolithically integrated semiconductorcomponent.

BACKGROUND INFORMATION

[0002] Monolithically integrated semiconductor components of the speciesare known. They include, for example, a vertical MOS (metal oxidesilicon) transistor that has a relatively lightly doped substrate regionof a first conductivity type and a more highly doped layer of the sameconductivity type for contacting (drain connection). Introduced into thesubstrate region is at least one conductivity region of oppositeconductivity type, which in each case surrounds a further conductivityregion of the first conductivity type.

[0003] This results in the formation of two PN transitions, of which afirst PN transition is short-circuited by a source connection. Appliedon the substrate surface is an MOS structure by means of which theregion of the second charge carrier regions close to the surface can beinverted, so that a conductive connection is created between the sourceconnection and drain connection. The second charge carrier region isconnected in electrically conductive fashion to the third charge carrierregion through the source connection (short-circuiting the first PNtransition), resulting in formation of a parasitic inverse diode. In anumber of circuit variants, this parasitic inverse diode thatnecessarily forms can be used as a freewheeling diode. For example, ifan inductive load is to be switched by means of the monolithicallyintegrated component, the freewheeling diode allows reverse commutationof the current. If the inductive load is, for example, triggered with abridge circuit made up of at least two MOS transistors that areconnected as pulse-width-modulated inverters in a boost chopper circuit,a first MOS transistor is triggered in pulsed fashion so that theinductive load either freewheels via the parasitic inverse diode of thefurther MOS transistor or is recharged via the activated second MOStransistor. The switching-on operation of the pulse-triggered MOStransistor is relevant in this context, since what can occur here isthat the inverse diode is energized and the charge is drained becausethe other MOS transistor is not conductive. This results in a so-calledcurrent breakdown situation that causes steep increases in ΔI/Δt. Thesein turn cause overvoltages and high-frequency oscillations that resultin undesirable interference effects.

[0004] It is known to connect, in parallel with the parasitic inversediodes, Schottky diodes that have a lower forward voltage. As a result,the parasitic inverse diodes remain inactive so that no stored chargeneeds to be drained out of the substrate region of the MOS transistors.It is known from European Published Patent Application No. 0 899 791 tointegrate the Schottky diodes into the monolithic component as parallelfreewheeling diodes, necessitating an additional charge carrierimplantation to establish a barrier. This additional charge carrierimplantation requires considerable technical outlay, however, therebyincreasing process costs.

SUMMARY OF THE INVENTION

[0005] The monolithically integrated semiconductor component, incontrast, the advantage that a Schottky diode connected in parallel withthe parasitic inverse diode can be implemented in simple fashion.Because the first charge carrier region includes a further contactingarea—that contacting area being additionally doped near the surface,depending on the doping concentration of the first charge carrierregion, with a further near-surface charge carrier region of higherconcentration, and being connected to the anode connection of the atleast one Schottky diode—it is possible to generate a shieldingstructure within the first charge carrier region if the additionalcontacting area is pulled to a potential above the potential of thesecond charge carrier region. It is thereby possible to reliably designthe so-called Schottky clamp for higher-inhibition MOS transistors, inwhich context a safety factor increase for the breakdown voltage (takinginto account the forward voltage tolerances) can be reduced andoptionally can be left out of consideration. Reducing the safety factorincrease on the breakdown voltage means that the additional voltagedrops which occur in conducting situations because of those safetyfactor increases are eliminated. The forward voltage tolerance thus hasno substantial influence on the junction voltage of the parasiticinverse diodes, which in the context of higher-inhibition MOStransistors remain below 650 mV in order to prevent forward operation ofthe parasitic inverse diodes.

[0006] The additional contacting area which is all that is provided inorder to implement the present invention can easily be achieved by aslight process modification in the manufacture of the monolithicallyintegrated semiconductor component, by the fact that upon deposition ofthe metallizations for the contact areas of the source connections, atleast one additional mask opening is simultaneously provided for theadditional contacting area. Additional process steps are thus notnecessary. All that is done is a change in the layout of the maskinglevel for manufacturing the metallizations.

[0007] The Schottky diode that can be incorporated into the circuitarrangement by way of the additional contacting area moreover yields areduction in power dissipation when the Schottky diode is inhibited orconductive. As a result of the shielding structure created beneath theadditional contacting area in the first charge carrier region, only arelatively small blocking voltage occurs across the Schottky diode, sothat the very high blocking-state currents typical of Schottky diodescan be greatly reduced or, conversely, a lower forward voltage can beachieved.

[0008] It is additionally advantageous that the Schottky diodes caneasily be adapted to the monolithically integrated semiconductorcomponent. The Schottky diode connected externally to the additionalcontacting area can, for example, be selected with regard to modifiedblocking voltage criteria or thermal criteria. Lastly, because it is noweasy to arrange the Schottky diode physically separately from the MOStransistor structure, the additional power dissipation of the Schottkydiode can occur in areas in which it does not contribute to heating ofthe monolithically integrated component. The fact that externalutilization of the Schottky diode is easily provided furthermore offersthe advantage that when MOS transistor structures are connected inparallel, it is not necessary to associate a separate Schottky diodewith each transistor structure, but instead a common Schottky diode canbe provided for multiple transistor structures.

BRIEF DESCRIPTION Of THE DRAWINGS

[0009]FIG. 1 is a schematic side view of a monolithically integratedcomponent according to the present invention.

[0010]FIG. 2 is another schematic side view of a monolithicallyintegrated component according to the present invention.

[0011]FIG. 3 is a schematic side view of a monolithically integratedcomponent according to the present invention.

[0012]FIG. 4 shows a first layout of the semiconductor componentaccording to the present invention.

[0013]FIG. 5 shows a second layout of the semiconductor componentaccording to the present invention.

[0014]FIG. 6 shows a third layout of the semiconductor componentaccording to the present invention.

[0015]FIG. 7 shows a fourth layout of the semiconductor componentaccording to the present invention.

[0016]FIG. 8 shows a fifth layout of the semiconductor componentaccording to the present invention.

[0017]FIG. 9 shows a sixth layout of the semiconductor componentaccording to the present invention.

DETAILED DESCRIPTION

[0018]FIG. 1 shows a monolithically integrated semiconductor component10 that is embodied as an MOS field effect transistor. Semiconductorcomponent 10 includes a drift region 12 having a first charge carrierdoping (for example, n-doped). Charge carrier regions 14 having a chargecarrier doping (in the example, p-doping) opposite to the first chargecarrier region (drift region) 12 are introduced into drift region 12.Further charge carrier regions 16 are integrated into charge carrierregions 14. Charge carrier regions 16 possess the same charge carrierdoping as charge carrier region 12, but are more highly doped (in theexample, n+-doped). Charge carrier region 12 is arranged on a layer 18that possesses the same charge carrier doping as charge carrier region12 but is more highly doped (in the example, n+-doped). Metallizations20 that short-circuit charge carrier regions 14 and 16 in the region oftheir PN transition 22 are patterned on the surface of semiconductorcomponent 10. A further metallization (contacting area) 26 is arranged,over an oxide that is not depicted, above PN transitions 24 betweencharge carrier regions 14 and 12. Metallization 26 extends over theentire channel region.

[0019] Charge carrier region 12 is equipped, by way of a highly dopedregion of the first conductivity type (in the example, n+-doped), with afurther metallization (contacting area) 28 that is located betweenadjacent PN transitions 24. A spacing a between metallization 28 and PNtransitions 24 is the same in each case. Metallization 28 is connectedto metallizations 20 via external Schottky diodes 30, metallization 28being connected in each case to the anodes of Schottky diodes 30.

[0020] Metallization 20 constitutes the source connection, layer 18 thedrain connection, and metallization 26 the gate connection of the MOStransistor. When a control voltage is applied to gate connection 26,near-surface conduction channels form in charge carrier regions 14 sothat source connection 20 is connected in electrically conductivefashion to drain connection 18, and the MOS transistor becomesconductive.

[0021] By way of the total spacing a+b+a of charge carrier regions 14,it is possible to define the blocking voltage through PN transition 24above which a near-surface region 32, more highly doped for contactingpurposes, of charge carrier region 12 remains at a fixed voltagepotential that is independent of any further rise in the drain voltage.The voltage potential in region 32 is thereby limited to ageometry-dependent constant (a+b+a). Schottky diodes 30 contacted viametallization 28 can thus be designed for a relatively low blockingvoltage that is determined by the voltage potential in region 32. Region32 thus constitutes a shielding structure for the electrical applicationof Schottky diodes 30, resulting in the aforementioned limiting of theblocking voltage. This simultaneously yields a reduction in theblocking-state currents and the power dissipation of Schottky diodes 30.In a manner known per se, Schottky diodes 30 can be used as freewheelingdiodes, for example for switching inductive loads in the bridge circuitmentioned at the outset.

[0022]FIG. 2 shows a modified embodiment, parts identical to those inFIG. 1 being labeled with the same reference characters and notexplained again. In contrast to the variant embodiment in FIG. 1, inwhich a source-side drain contact is implemented, in FIG. 2 a draincontact is implemented on the channel side (conductive channel throughcharge carrier regions 14 upon activation of metallizations 26). Thereader is referred to the description of FIG. 1 as regards function.

[0023]FIG. 3 shows a variant embodiment in which buried charge carrierregions 34 that contain the same charge carrier doping as charge carrierregions 14 are arranged between charge carrier regions 14. Chargecarrier regions 34 are arranged in a grid pattern, resulting inconnections 36, as indicated here, between charge carrier regions 14.Buried structures 34 and conductive connections 36 cause the formationof a JFET structure (known per se) that in this case takes over ashielding structure of region 32. Any rise in potential in region 32 isthereby also limited, resulting in the aforementioned reduction in theblocking voltage of Schottky diodes 30.

[0024]FIGS. 4 through 9 schematically show, in plan view, a number ofvariant layouts of component 10. FIGS. 4 through 6 relate to a so-calledstrip design, while FIGS. 7 through 9 concern a so-called cell design.The individual doping regions are labeled with the reference charactersexplained in FIGS. 1 through 3, and the reader is therefore referred tothose Figures as regards the arrangement.

[0025]FIG. 4 through 7 correspond to FIG. 1,Figures 5 through 8 to FIG.2, and FIGS. 6 and 9 to FIG. 3.

1. A monolithically integrated semiconductor component, having a firstcharge carrier region (12) of a first charge carrier doping; at leasttwo second charge carrier regions (14) with opposite charge carrierdoping, patterned within the first charge carrier region (12) at aspacing from one another; and third charge carrier regions (16), withthe first charge carrier doping, patterned within the second chargecarrier regions (14), a PN transition (22) being short-circuited betweenthe second charge carrier regions (14) and the third charge carrierregions (16) via a contacting area (20) (source connection), the firstcharge carrier region (12) being equipped with a contact (18) (drainconnection), and the second charge carrier regions (14) being invertableby way of a contacting area (26) in the region between the first chargecarrier region (12) and the third charge carrier region (16); and havingat least one Schottky diode (30) connected in parallel with the chargecarrier region (12) and the charge carrier region (16), wherein afurther contacting area (28) is applied onto the first charge carrierregion (12), and this contacting area (28) has associated with it afurther charge carrier region (32) that is more highly doped as comparedto the doping concentration of the first region (12) so that an ohmiccontact is created, and the latter is connected to the anode connectionof the at least one Schottky diode (30).
 2. The semiconductor componentas defined in claim 1, wherein the contacting area (28) is positioned inthe region of a shielding structure (32) that is established when adrain voltage is applied.
 3. The semiconductor component as defined inone of the foregoing claims, wherein the shielding structure (32) isdefined by a spacing (a+b+a) of PN transitions (24) of adjacent secondcharge carrier regions (14).
 4. The semiconductor component as definedin one of the foregoing claims, wherein the semiconductor component (10)has a source-side drain contact (18).
 5. The semiconductor component asdefined in one of claims 1 through 3, wherein the semiconductorcomponent (10) has a channel-side drain contact (18).
 6. Thesemiconductor component as defined in one of the foregoing claims,wherein the shielding structure (32) is defined by a buried JFETstructure (34, 36).